The use of self-aligned contacts in the HBT process is intended to minimize the base access resistance of the device. The use of this technique is known in that fabrication of early HBTs utilized contact lithography or early broadband wafer stepper systems for device fabrication. These systems are capable of limited layer-to-layer registration and therefore, the only technique available to minimize contact spacing was to employ the technique of self-aligned contacts. Large circuit demonstrating yield of known devices is described in T. P. Broekaert, W. Ng, J. F. Jensens, D, Yap, D. L. Persechini, S. Bourgholtaer, C. H. Fields, Y. K. Brown-Boegeman, B. Shi, and R. H. Walden, “InP-HBT Optoelectronic Integrated Circuits for Photonic Anaolog-to-digital Conversion”, IEEE Journal of Solid-State Circuits, Vol. 36, No. 9, September 2001, pp. 1335-1342, which is incorporated herein by reference.
While self-aligned HBT devices do demonstrate lower base resistance, this technique is prone to variations in device Beta due to lateral diffusion of minority carriers in the base and recombination at the base metal (BMET) contact which leads to variations in the base current of these devices. Since variations in base current lead to variations in Beta, the HBTs fabricated using self-aligned contacts demonstrate a large range of measured Beta.
A description of general HBT devices can be found in Jensen, J. F.; Stanchina, W. E.; Metzger, R. A.; Rensch, D. B.; Pierce, M. W.; Kargodorian, T. V.; Allen, Y. K., “AlInAs/GaInAs HBT IC technology”, Custom Integrated Circuits Conference, 1990, Proceedings of the IEEE 1990, 13-16 May 1990, Pages: 18.2/1-18.2/4, which is incorporated herein by reference.
Another general description of a HBT device is disclosed by Hafizi, M.; Stanchina, W. E.; Sun, H. C., “Submicron fully self-aligned AlInAs/GaInAs HBTs for low-power applications”, Device Research Conference, 1995. Digest. 1995 53rd Annual, 19-21 Jun. 1995, Pages: 80-81, which is incorporated herein by reference.
Jensen, J. F.; Stanchina, W. E.; Metzger, R. A.; Rensch, D. B.; Allen, Y. K.; Pierce, M. W.; Kargodorian, T. V, “High speed dual modulus dividers using AlInAs—GaInAs HBT IC technology”, Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1990. Technical Digest 1990, 12th Annual, 7-10 Oct. 1990, Pages 41-44 describe a general HBT device as well, which is incorporated herein by reference.
Base-emitter shorts are a leading limitation to HBT IC yield. Shorts due to metal spiting during the self-aligned base metal deposition occurs in about 1 in 600 transistors and limits current HBT IC yield to below 2000 transistors. The use of non-self-aligned emitter-base contacts eliminates the possibility of shorting of this type.
In HBTs designed for high-speed applications, current gain is not determined solely by recombination in the bulk of the base epitaxial layer. Both surface and bulk components of base current combine to decrease the overall device current gain. InP HBTs known in the state of the art employ self-aligned base-emitter structures to reduce the extrinsic base resistance and the base-collector junction capacitance. This alignment technique results in narrow contact spacing and potentially large values of surface recombination. Handbook of III-V Heterojunction Bipolar Transistors, W. Liu, 1998 Wiley & Sons, FIGS. 3-54 & 3-55 shows that Beta is extremely sensitive to the spacing of the emitter and base contacts for values closer than about 1500 Å. In this range, minor variations in wet etch isotropy or in metal deposition source angle could lead to wildly varying values of Beta. In a self-aligned HBT, the emitter-base spacing can even approach zero.
The mechanism for reduction and variation in Beta is shown in FIG. 1. FIG. 1 shows that electrons, which are emitted by the emitter epitaxial layer 2, migrate through the base layer 1 to the collector layer 5. A minority of the electrons however laterally diffuse and do not reach the collector layer 5 and instead migrate to the base metal 4. Any electron that reaches the base metal 4 instead of collector layer 5 causes a reduction and variation in device Beta.
FIG. 11 is a schematic depiction of a state-of-the-art self-aligned (SA) transistor that is currently being fabricated according to the prior art. The BMET layer 4 is a large square which completely overlays the emitter metal (EMET) 3 pattern. The current, known process of manufacturing the SA transistor is shown in FIG. 6 to FIG. 11. First, a patterned emitter metal layer 2 is formed to yield an emitter metal cap 3 as shown in FIG. 6. This process can be carried out in two different ways. According to one method (1) a photoresist 4 is applied on the emitter layer and (2) exposed through a mask and (3) the exposed photoresist 4 is removed leaving a space pattern in the photoresist 4 for the emitter metal cap 3 and (4) emitter metal is deposited on the top surface of the wafer and (5) the photoresist 4 and the emitter metal covering the photoresist 4 is removed leaving the emitter metal cap 3 and the base layer 1. According to a second method (1) an emitter metal layer is deposited on the emitter epitaxial layer 2, (2) photoresist is applied on the emitter metal layer, and (3) exposed through a mask and (4) the exposed photoresist 4 is removed leaving a photoresist 4 on the emitter metal layer for the emitter metal cap 3 and (4) emitter metal which is not covered by the photoresist 4 is removed and (5) the photoresist 4 covering the emitter metal cap 3 is removed leaving the emitter metal cap 3 and the base layer 1.
In a further process step the emitter epitaxial layer 2 is etched off to yield an emitter epitaxy 2 below and in line with emitter metal cap 3. FIG. 7 shows an emitter epitaxy 2 below and in line with the emitter metal cap 3, wherein the emitter epitaxy has an undercut Δ. The undercut Δ is obtained by two etch process steps, a wet etch and a dry etch. The undercut Δ is necessary for devices according to the prior art between the base metal 4 and the emitter epitaxy 2 as shown in FIGS. 10 and 11. The emitter epitaxy 2 is in the form of a pedestal and together with the overlying emitter metal cap 3 form the emitter electrode of the HBT. In a next step, a photoresist layer 8 is applied on the base layer 1 covering the base layer 1 and emitter epitaxy 2 and emitter metal cap 3 as shown in FIG. 8.
The next process is carried out according to image reversal photolithography as follows. The photoresist layer 8 is irradiated by light or electron beam 10 through a mask 9. The mask 9 covers the area overlying the emitter metal cap 3 that is thus not irradiated. After irradiation, the surface of the photoresist layer 8 that was irradiated through the mask 9 becomes impervious to removal. The area of the photoresist 8 that was covered and therefore not irradiated is susceptible to removal, as shown in FIG. 8. After removing the susceptible area of the photoresist 8, part of the base layer 1, the emitter epitaxy 2 and the emitter metal cap 3 are no longer covered by the photoresist layer 8 and are thus exposed, as shown in FIG. 9. In the next step, base metal 4 is applied on the entire top surface as shown in FIG. 10. In the next step the photoresist 8 is removed together with the base metal 4 on top of the photoresist 8 as shown in FIG. 11. The emitter electrode comprised of emitter epitaxy 2 and emitter metal cap 3 is covered by the base metal 4. The base metal 4 is spaced a certain distance from the emitter epitaxy 2 in order to avoid electrical shorting between the base metal 4 and the emitter epitaxy 2. Such shorting is avoided by the provision of the emitter epitaxy 2 undercut Δ. However, due to the undercut Δ of the emitter epitaxy 2, the contact area between the emitter epitaxy 2 and the emitter metal cap 3 is reduced.
It is therefore desirable to be able to produce an HBT that reduces shorting between the base metal 4 and the emitter epitaxy 2, that solves the recurring problem of low and varying values of current gain (Beta), and that further solves the problem of variations in HBT Beta from wafer to wafer, variations in HBT Beta within a single wafer and from wafer to wafer. Base emitter shorts, which occur in about 1 our of every 600 transistors, lead to poor line yield for HBT wafers.